/*
 * ram.v
 *
 * Copyright 2024 dh33ex <dh33ex@riseup.net>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA or visit <http://www.gnu.org/licenses/>.
 *
 *
 */

module ram(
    input                i_rst,
    input                i_clk,

    input       [31:0]   i_addr,
    input       [31:0]   i_wd,
    input                i_we,

    output      [31:0]   o_rd
);

    reg [31:0]  RAM[256:283];

    always @(posedge i_clk) begin
        if (i_we && i_addr >= 32'h400 && i_addr < 32'h470) begin
            RAM[i_addr[31:2]] <= i_wd;
        end
    end

    assign o_rd = RAM[i_addr[31:2]];

endmodule
